Gate-dielectric stack engineering for high-mobility and low-noise SiMOS quantum devices
Published in npj Quantum Information
Md. Mamunur Rahman, Ensar Vahapoglu, Kok Wai Chan, Tuomo Tanttu, Ajit Dash, Jonathan Yue Huang, Steve Yianni, Venkatesh Chenniappan, Jesús D. Cifuentes, Fay E. Hudson, Christopher C. Escott, Yik Kheng Lee, Nard Dumoulin Stuyck, Arne Laucht, Andrea Morello, Andre Saraiva, Jared H. Cole, Andrew S. Dzurak, Wee Han Lim
Abstract
We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal-oxide-semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies show that varying the oxidant (H2O or D2O) during ALD Al2O3 growth has very little influence on mobility, whereas increasing the Al2O3 deposition temperature from 200 °C to 300 °C yields a modest improvement. Devices incorporating HfO2 exhibit enhanced carrier mobility, possibly due to defect passivation associated with aluminum diffusion into the dielectric from the gate metal. In contrast, gate-metal selection strongly influences transport properties, with TiPd-gated devices exhibiting substantially lower mobility than their Al-gated counterparts. Charge-noise measurements further reveal a clear correlation between mobility and noise performance, with lower-mobility devices generally exhibiting higher charge noise, while the poly-Si-gated CMOS-foundry device achieves the lowest noise level. Finally, dual-feedback dot-sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.
